However running "coreinfo" (sysinternals) tells me another story - that prefetchw and all other CPU prerequisites ARE INDEED met by my Pentium 4. Inclined to believe this as the 64 bit Windows 8.0 runs just fine. What gives?
Hello JakeThePeg57,
If my understanding is right, you can install Windows 8, but when you try to upgrade to Windows 8.1, you receive the error message about the CPU doesnt meet.
Do you upgrade to Windows 8.1 by Windows store?
Before the upgrade, please get the latest critical and important updates and temporarily turn off the antivirus program.
For more information, please take a look at the following article about updating to Windows 8.1 from Windows 8.
http://windows.microsoft.com/en-hk/windows-8/update-from-windows-8-tutorial
Best regards,
Fangzhou CHEN
Hi CHEN,
Thanks for your reply. I need to be more clear...
I wrote...
*The installer claims that the CPU doesn't support PREFETCHW instruction and aborts.*
This message did indeed come from an upgrade attempt from Windows 8.0 x64 standard edition (and I had just installed that fresh (as a clean install) from iso image that I downloaded from the windows store using the upgrade assistant. Your reply might indicate that I have some mileage in trying this approach again AFTER installing critical & important updates and turning windows firewall off temporarily.
I also wrote..
*using iso images downloaded with my product key.*
I gave up on the upgrade route and downloaded iso images instead using the Media Creation Tool to USB ISO images of Windows 8.0 and Windows 8.1 Standard x64.
Windows 8.0 installs and runs just fine using clean install from USB ISO image.
WINDOWS 8.1 install consistently fails during installation...
The following error message is flashed on the screen (captured by video)
Your PC needs to restart.
Please hold down the power button:
Error Code: 0x000000C4
Parameters:
0x0000000000000091
0x000000000000000F
0xFFFFF80212FC0A00
0X0000000000000000
BIOS offers me control over hyperthreading on/off but the setting has no influence on this behaviour.
===========
Here is what coreinfo has to say about my CPU....
Coreinfo v3.31 - Dump information on system CPU and memory topology
Copyright (C) 2008-2014 Mark Russinovich
Sysinternals -
Intel(R) Pentium(R) 4 CPU 3.00GHz
x86 Family 15 Model 4 Stepping 9, GenuineIntel
Microcode signature: 00000003
HTT * Hyperthreading enabled
HYPERVISOR - Hypervisor is present
VMX - Supports Intel hardware-assisted virtualization
SVM - Supports AMD hardware-assisted virtualization
X64 * Supports 64-bit mode
SMX - Supports Intel trusted execution
SKINIT - Supports AMD SKINIT
NX * Supports no-execute page protection
SMEP - Supports Supervisor Mode Execution Prevention
SMAP - Supports Supervisor Mode Access Prevention
PAGE1GB - Supports 1 GB large pages
PAE * Supports > 32-bit physical addresses
PAT * Supports Page Attribute Table
PSE * Supports 4 MB pages
PSE36 * Supports > 32-bit address 4 MB pages
PGE * Supports global bit in page tables
SS * Supports bus snooping for cache operations
VME * Supports Virtual-8086 mode
RDWRFSGSBASE - Supports direct GS/FS base access
FPU * Implements i387 floating point instructions
MMX * Supports MMX instruction set
MMXEXT - Implements AMD MMX extensions
3DNOW - Supports 3DNow! instructions
3DNOWEXT - Supports 3DNow! extension instructions
SSE * Supports Streaming SIMD Extensions
SSE2 * Supports Streaming SIMD Extensions 2
SSE3 * Supports Streaming SIMD Extensions 3
SSSE3 - Supports Supplemental SIMD Extensions 3
SSE4a - Supports Streaming SIMDR Extensions 4a
SSE4.1 - Supports Streaming SIMD Extensions 4.1
SSE4.2 - Supports Streaming SIMD Extensions 4.2
AES - Supports AES extensions
AVX - Supports AVX intruction extensions
FMA - Supports FMA extensions using YMM state
MSR * Implements RDMSR/WRMSR instructions
MTRR * Supports Memory Type Range Registers
XSAVE - Supports XSAVE/XRSTOR instructions
OSXSAVE - Supports XSETBV/XGETBV instructions
RDRAND - Supports RDRAND instruction
RDSEED - Supports RDSEED instruction
CMOV * Supports CMOVcc instruction
CLFSH * Supports CLFLUSH instruction
CX8 * Supports compare and exchange 8-byte instructions
CX16 * Supports CMPXCHG16B instruction
BMI1 - Supports bit manipulation extensions 1
BMI2 - Supports bit manipulation extensions 2
ADX - Supports ADCX/ADOX instructions
DCA - Supports prefetch from memory-mapped device
F16C - Supports half-precision instruction
FXSR * Supports FXSAVE/FXSTOR instructions
FFXSR - Supports optimized FXSAVE/FSRSTOR instruction
MONITOR * Supports MONITOR and MWAIT instructions
MOVBE - Supports MOVBE instruction
ERMSB - Supports Enhanced REP MOVSB/STOSB
PCLMULDQ - Supports PCLMULDQ instruction
POPCNT - Supports POPCNT instruction
LZCNT - Supports LZCNT instruction
SEP * Supports fast system call instructions
LAHF-SAHF * Supports LAHF/SAHF instructions in 64-bit mode
HLE - Supports Hardware Lock Elision instructions
RTM - Supports Restricted Transactional Memory instructions
DE * Supports I/O breakpoints including CR4.DE
DTES64 * Can write history of 64-bit branch addresses
DS * Implements memory-resident debug buffer
DS-CPL * Supports Debug Store feature with CPL
PCID - Supports PCIDs and settable CR4.PCIDE
INVPCID - Supports INVPCID instruction
PDCM - Supports Performance Capabilities MSR
RDTSCP - Supports RDTSCP instruction
TSC * Supports RDTSC instruction
TSC-DEADLINE - Local APIC supports one-shot deadline timer
TSC-INVARIANT - TSC runs at constant rate
xTPR * Supports disabling task priority messages
EIST - Supports Enhanced Intel Speedstep
ACPI * Implements MSR for power management
TM * Implements thermal monitor circuitry
TM2 - Implements Thermal Monitor 2 control
APIC * Implements software-accessible local APIC
x2APIC - Supports x2APIC
CNXT-ID * L1 data cache mode adaptive or BIOS
MCE * Supports Machine Check, INT18 and CR4.MCE
MCA * Implements Machine Check Architecture
PBE * Supports use of FERR#/PBE# pin
PSN - Implements 96-bit processor serial number
PREFETCHW - Supports PREFETCHW instruction
Maximum implemented CPUID leaves: 00000005 (Basic), 80000008 (Extended).
Logical to Physical Processor Map:
** Physical Processor 0 (Hyperthreaded)
Logical Processor to Socket Map:
** Socket 0
Logical Processor to NUMA Node Map:
** NUMA Node 0
No NUMA nodes.
Logical Processor to Cache Map:
** Data Cache 0, Level 1, 16 KB, Assoc 8, LineSize 64
** Unified Cache 0, Level 2, 1 MB, Assoc 8, LineSize 128
Logical Processor to Group Map:
** Group 0
That output from CoreInfo shows that PREFETCHW is not available on your processor. * means that your processor supports that function, - means that it does not.
Brandon
Windows Outreach Team- IT Pro
Windows for IT Pros on TechNet